MSI MS-6382 Especificaciones descargar pdf (Pagina 45)

Chapter 3

3-14

DRAM Timing by SPD Selects whether DRAM timing is controlled

by the SPD EPROM on the DRAM card.

Setting to No not only makes DRAM

Frequency, SDRAM CAS Latency and Bank

Interleave adjustable but also sets SDRAM

Precharge/RAS to CAS/RAS Pulse to

3T/3T/6T.

DRAM Frequency (MHz) The chipset supports synchronous and

asynchronous mode between host clock and

DRAM clock frequency. The settings are:

Auto: BIOS automatically determines the DRAM

clock frequency.

HCLK+33: The DRAM clock will be equal to Host

Clock plus 33MHz. For example, if the Host

Clock is 100MHz, the DRAM clock will be

133MHz.

HCLK: The DRAM clock will be equal to the Host

Clock.

HCLK-33: The DRAM clock will be equal to the Host

Clock minus 33MHz. For example, if the

Host Clock is 133MHz, the DRAM clock will

be 100MHz.

SDRAM CAS Latency Controls the time delay (in clock cycles)

before SDRAM starts a read command after

receiving it. Settings are Auto, 2, 2.5 and 3.

Bank Interleave Enables or disables bank interleave feature.

Settings are Auto and Disabled.

Current Host (FSB) Clock: Displays current host clock frequency.

Current DRAM Frequency:Displays current DRAM clock frequency.

Current DDR Frequency: This display-only filed appears only when

DDR DRAMs are installed.

AGP & P2P Bridge Control

Press <Enter> to enter the sub-menu. You will see a sub-menu screen similar

to the following:

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MSI MS-6382 Especificaciones Pagina 45